The most recent generation of high performance processes contain tightly packed transistors in a CMOS environment. The performance of the transistors in such an environment is compromised by drain-source current leakage. This may permanently damage the transistor and the entire CMOS environment, for example by thermal damage if the current leakage is allowed to heat the chip beyond its normal operating temperature range.
Current leakage is due to short-channel effects, and low device threshold voltages, for example 0.3 V, compatible with low-voltage operation. As a result of the requirement of having high packing density design of the transistors, the polysilicon gate oxide of the transistor is ultra thin or relatively narrow, for example 10 Å to 20 Å, compared with gate thickness of earlier conventional transistors, for example 35 Å to 100 Å. The gate may break down creating a leakage path between channel and gate, or drain to source. In extreme cases, due to the fact that leakage current increases rapidly with temperature, the IC or chip may be permanently damaged. The cumulative leakage current from multiple transistors may become large enough exceed the device package temperature limits and damage the IC.
As semiconductor integrated circuits continue to decrease in scale and packing density of transistors is on the rise, the problems associated with drain-source current leakage is having greater impact on CMOS IC performance.
There is a need for an apparatus and method for detecting and controlling excess current leakage of a CMOS device.